1. Field of the Invention
The present invention relates to a differential amplifier with a high slew rate.
2. Description of Related Art
In recent years, a liquid crystal display increasingly has a larger screen and a higher definition. Consequently, a liquid crystal display is provided with a greater number of differential amplifier circuits for example. A source driver provided in a liquid crystal display is required to have a capacity to drive a greater load faster without increasing power consumption.
Japanese patent application No. JP-P 2005-175994A (Patent literature 1: corresponding to U.S. Pat. No. 7,199,662 (B2)) discloses an output circuit which reduces a consumption current of an operational amplifier and which reduces distortion of an output waveform of the operational amplifier. The output circuit according to the patent literature 1 will be described below with reference to FIGS. 1 to 3.
FIG. 1 is a circuit diagram showing a push-pull output operational amplifier 1 provided in a one-amplifier output circuit according to the patent literature 1. The operational amplifier 1 in FIG. 1 outputs both a rising waveform and a falling waveform. FIG. 1 shows one of a plurality of operational amplifiers provided in the output circuit. The operational amplifier 1 has a terminal 11 and a terminal 12. The terminal 11 supplies a bias voltage VbiasA to an N-channel MOS transistor Q5 provided in the operational amplifier 1. The terminal 12 supplies a bias voltage VbiasB to a P-channel MOS transistor Q15 provided in the operational amplifier 1. The operational amplifier 1 improves a slew rate at the time of rising and falling of an output signal, by being supplied with the bias voltages VbiasA and VbiasB to the terminals 11 and 12 respectively.
FIG. 2 is a circuit diagram showing a bias circuit 2 in the patent literature 1. The bias circuit 2 supplies the bias voltages VbiasA and VbiasB to the operational amplifier 1. The bias circuit 2 supplies the bias voltage VbiasA to the terminal 11 of the operational amplifier 1 through an N-bias line 25. The bias circuit 2 supplies the bias voltage VbiasB to the terminal 12 of the operational amplifier 1 through a P-bias line 26. The bias circuit 2 has a bias current source 21, a bias voltage obtaining circuit 22, a precharge circuit 23, and a precharge power source 24.
The bias current source 21 is a low-bias bias current source without switching of a high bias and a low bias. The bias current source 21 includes a P-channel MOS transistor Q21. The bias current source 21 is set to meet a condition that on-state resistance R1 can control the operational amplifier so that the operational amplifier has a low bias.
The bias voltage obtaining circuit 22 has N-channel MOS transistors Q23, Q24, and Q27, and P-channel MOS transistors Q25 and Q26. The MOS transistor Q23 is connected between the bias current source 21 and a low-voltage-side terminal VSS. The MOS transistor Q24 is connected to the MOS transistor Q23 through mirror connection. The MOS transistor Q25 is connected in series to the MOS transistor Q24 between a high-voltage-side terminal VDD and the low-voltage-side terminal VSS. The MOS transistor Q26 is connected to the MOS transistor Q25 through mirror connection. The MOS transistor Q27 is connected in series to the MOS transistor Q26 between the high-voltage-side terminal VDD and the low-voltage-side terminal VSS. The series connection point between the MOS transistors Q26 and Q27 serves as output to the N-bias line 25. The series connection point between the MOS transistors Q24 and Q25 serves as output to the P-bias line 26.
The precharge circuit 23 has precharge capacitors Cn and Cp, an N-channel MOS transistor Q28, and a P-channel MOS transistor Q29. The capacitor Cn is connected between the low-voltage-side terminal VSS and the series connection point between the MOS transistors Q26 and Q27. The capacitor Cp is connected between the high-voltage-side terminal VDD and the series connection point between the MOS transistors Q24 and Q25. The N-channel MOS transistor Q28 supplies a precharge voltage Vpn from the precharge power source 24 to the capacitor Cn. The P-channel MOS transistor Q29 supplies a precharge voltage Vpp from the precharge power source 24 to the capacitor Cp. The MOS transistor Q28 is controlled by a timing signal Tp. The MOS transistor Q29 is controlled by an inversion signal of the timing signal Tp through an inverter INV.
The precharge power source 24 outputs the precharge voltages Vpn and Vpp. The precharge voltages Vpn and Vpp are adjusted at desired voltages by control signals (not shown).
FIG. 3 is a timing chart showing operations of the operational amplifier 1 and the bias circuit 2 in the patent literature 1. The capacitors Cn and Cp start electric charge with the precharge power source 24 at time T1 when a pulse waveform of the timing signal Tp rises. Consequently, the bias circuit 2 outputs a high bias voltage. The capacitors Cn and Cp start electric discharge at time T2 when the pulse waveform of the timing signal Tp falls.
At the time T2, the operational amplifier 1 starts rising and falling of output waveforms. At this time, the output waveforms of the operational amplifier 1 steeply rise and fall due to a high bias from the bias circuit 2. The bias voltage from the bias circuit 2 shifts from a high bias to a low bias based on curves of CR time constants of discharge paths of the capacitors Cn and Cp. Therefore, a high slew rate shifts to a low slew rate as rising and falling of an output wave form come closer to a given voltage, making it possible to reduce distortion of an output waveform.
Bias voltages at the time of rising and falling of an output waveform of the operational amplifier 1 are attenuated at curves of CR time constants of discharge paths of the capacitors Cn and Cp. For this reason, a consumption current of the operational amplifier 1 is reduced compared with an output circuit to which a high bias of the same level is supplied over a given period of time. It is also possible to minutely set control of bias currents at the time of rising and falling of an output waveform of the operational amplifier 1 since the precharge voltages Vpn and Vpp from the precharge power source 24 are variable.
The inventor has now discovered the following facts. However, there is a possibility that the bias circuit 2 in the patent literature 1 causes oscillation of the operational amplifier 1. This is because in the bias circuit 2 in the patent literature 1, a time period during which a bias voltage is high is long since a bias voltage is increased once before the polarity of an amplifier output is inverted. In addition, the consumption current during a time period in which the timing signal Tp is at a high level is greater since a time period during which a bias voltage is high is long.